Renesas Electronics /R7FA6M3AH /EPTPC0 /SYRVLDR

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Interpret as SYRVLDR

BMUP=0, STUP=0, ANUP=0

Description

SYNFP Register Value Load Directive Register

Fields

BMUP	BMC Update 0 (0): no effect 1 (1): Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information.
STUP	State Update 0 (0): no effect 1 (1): Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages.
ANUP	Announce Message Generation Information Update 0 (0): no effect 1 (1): Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages.

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